Masaya Nakano

Publication Activity (10 Years)

Years Active: 2005-2022
Publications (10 Years): 5

Top Topics

Write Operations

Resource Utilization

Top Venues

IEEE J. Solid State Circuits

Publications

Masaya Nakano, Yoshinobu Kaneda, Satoru Nakanishi, Yasumitsu Murai, Yosuke Tashiro, Yasuhiko Taito, Tomoya Ogawa, Hidenori Mitani, Takashi Ito, Takashi Kono
Density With Charge-Assisted Offset Cancellation Sense Amplifier. IEEE J. Solid State Circuits 57 (10) (2022)
Masaya Nakano, Yoshinobu Kaneda, Koichi Takeda, Takahiro Shimoi, Yasunobu Aoki, Satoru Nakanishi, Yosuke Tashiro, Yasuhiko Taito, Ken Matsubara, Munekatsu Nakagawa, Tomoya Ogawa, Takashi Kurafuji, Hidenori Mitani, Takashi Ito, Takashi Kono
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier. A-SSCC (2021)
Akihiko Kanda, Takashi Kurafuji, Koichi Takeda, Tomoya Ogawa, Yasuhiko Taito, Kazuo Yoshihara, Masaya Nakano, Takashi Ito, Hiroyuki Kondo, Takashi Kono
A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive. VLSI Circuits (2019)
Yasuhiko Taito, Takashi Kono, Masaya Nakano, Tomoya Saito, Takashi Ito, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C. IEEE J. Solid State Circuits 51 (1) (2016)
Yasuhiko Taito, Masaya Nakano, Hiromi Okimoto, Daisuke Okada, Takashi Ito, Takashi Kono, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C. ISSCC (2015)
Kiyohiro Furutani, Takeshi Hamamoto, Takeo Miki, Masaya Nakano, Takashi Kono, Shigeru Kikuda, Yasuhiro Konishi, Tsutomu Yoshihara
Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories. IEICE Trans. Electron. (2) (2005)