Masakazu Aoki

Publication Activity (10 Years)

Years Active: 1993-2008
Publications (10 Years): 0

Publications

Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda
Concise Modeling of Transistor Variations in an LSI Chip and Its Application to SRAM Cell Sensitivity Analysis. IEICE Trans. Electron. (4) (2008)
Hiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki
Challenge: variability characterization and modeling for 65- to 90-nm processes. CICC (2005)
Masakazu Aoki, Shin-ichi Ohkawa, Hiroo Masuda
Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an Lsi Chip. IEICE Trans. Electron. (5) (2005)
Hiroo Masuda, Shin-ichi Ohkawa, Masakazu Aoki
Approach for physical design in sub-100 nm era. ISCAS (6) (2005)
Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. IEEE J. Solid State Circuits 34 (8) (1999)
Youji Idei, Katsuhiro Shimohigashi, Masakazu Aoki, Hiromasa Noda, Hidetoshi Iwai, Katsuyuki Sato, Tadashi Tachibana
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register. IEEE J. Solid State Circuits 33 (2) (1998)
Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki
Low-noise, high-speed data transmission using a ringing-canceling output buffer. IEEE J. Solid State Circuits 30 (12) (1995)
Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid State Circuits 30 (11) (1995)
Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki
A charge recycle refresh for Gb-scale DRAM's in file applications. IEEE J. Solid State Circuits 29 (6) (1994)
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's. IEEE J. Solid State Circuits 29 (8) (1994)
Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa
Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs. IEEE J. Solid State Circuits 29 (4) (1994)
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
Subthreshold-current reduction circuits for multi-gigabit DRAM's. IEEE J. Solid State Circuits 29 (7) (1994)
Takao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito
synapse neural network. IEEE Trans. Neural Networks 4 (3) (1993)