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Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's.

Takeshi SakataKiyoo ItohMasashi HoriguchiMasakazu Aoki
Published in: IEEE J. Solid State Circuits (1994)
Keyphrases
  • low voltage
  • power line
  • selection scheme
  • selection algorithm
  • design considerations
  • tree crown
  • power management
  • immune genetic algorithm
  • image processing
  • cmos technology