Masashi Horiguchi

Publication Activity (10 Years)

Years Active: 1994-2020
Publications (10 Years): 1

Top Topics

Top Venues

Publications

Lei Sha, Anna Kuwana, Masashi Horiguchi, Haruo Kobayashi
Simple Reference Voltage Generation Circuit Insensitive to Temperature. ISOCC (2020)
Shinya Sano, Yasuhiko Takahashi, Masashi Horiguchi, Moriyoshi Ota
A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from -50°C to +150°C using piecewise-linear-current curvature compensation. VLSIC (2012)
Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. CICC (2011)
Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka
Low-voltage limitations of memory-rich nano-scale CMOS LSIs. ESSCIRC (2007)
Kiyoo Itoh, Masashi Horiguchi, Takayuki Kawahara
Ultra-low voltage nano-scale embedded RAMs. ISCAS (2006)
Yoshinobu Nakagome, Masashi Horiguchi, Takayuki Kawahara, Kiyoo Itoh
Review and future prospects of low-voltage RAM circuits. IBM J. Res. Dev. 47 (5-6) (2003)
Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki
Low-noise, high-speed data transmission using a ringing-canceling output buffer. IEEE J. Solid State Circuits 30 (12) (1995)
Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid State Circuits 30 (11) (1995)
Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki
A charge recycle refresh for Gb-scale DRAM's in file applications. IEEE J. Solid State Circuits 29 (6) (1994)
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's. IEEE J. Solid State Circuits 29 (8) (1994)
Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki
Subthreshold-current reduction circuits for multi-gigabit DRAM's. IEEE J. Solid State Circuits 29 (7) (1994)