Akira Kotabe

Publication Activity (10 Years)

Years Active: 2001-2012
Publications (10 Years): 0

Top Topics

Recognition Scheme

Top Venues

IEICE Trans. Electron.

Publications

Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh
Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays. IEICE Trans. Electron. (4) (2012)
Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device. IEICE Trans. Electron. (4) (2012)
Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh
Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing. IEICE Trans. Electron. (4) (2012)
Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device. ISCAS (2012)
Akira Kotabe, Kiyoo Itoh, Riichiro Takemura
0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs. IEICE Trans. Electron. (4) (2012)
Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi
Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. CICC (2011)
Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa
1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. IEEE J. Solid State Circuits 46 (4) (2011)
Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi
CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays. IEEE J. Solid State Circuits 45 (11) (2010)
Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh
Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. ISSCC (2009)
Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. ISSCC (2007)
Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya
Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node. IEEE J. Solid State Circuits 42 (6) (2007)
Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh
A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. IEEE J. Solid State Circuits 40 (4) (2005)
Tadayoshi Enomoto, Akira Kotabe
A fast motion estimation algorithm and low-power 0.13-um CMOS motion estimation circuits. ISCAS (2) (2001)