Kenichi Osada

Publication Activity (10 Years)

Years Active: 1996-2015
Publications (10 Years): 0

Top Topics

Learning Design

Data Conversion

Retrieval Effectiveness

Top Venues

Publications

Takashi Takemoto, Yasunobu Matsuoka, Yoshikazu Sugiyama, Hidenori Yonezawa, Hiroki Yamashita, Koichiro Adachi, Takahiro Nakamura, Etsuko Nomoto, Kouji Nakahara, Hideo Arimoto, Kenichi Osada, Tatemi Ido
A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver. OFC (2015)
Yasuhiro Shinozuka, Hiroshi Fuketa, Koichi Ishida, Futoshi Furuta, Kenichi Osada, Kenichi Takeda, Makoto Takamiya, Takayasu Sakurai
Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme. ISQED (2013)
Kiyoto Ito, Makoto Saen, Kenichi Osada
Scalable robotic-hand control system based on a hierarchical multi-processor architecture adopting a large number of tactile sensors. IROS (2012)
Ming Liu, Tatsuo Nakagawa, Kenichi Osada
Fully digital voltage-mode control based on predictive hysteresis method (FDVC-PH) for DC-DC converters. ISCAS (2012)
Futoshi Furuta, Kenichi Osada
, 3D interconnect using adaptive timing control and low capacitance TSV. 3DIC (2011)
Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda
Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 19 (10) (2011)
Kiichi Niitsu, Yoshinori Kohama, Yasufumi Sugimori, Kazutaka Kasuga, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration. IEEE Trans. Very Large Scale Integr. Syst. 18 (8) (2010)
Kiyoto Ito, Makoto Saen, Kenichi Osada, Tomoyuki Kodama, Hiroyuki Mizuno
Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. 3DIC (2010)
Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits 45 (4) (2010)
Naoto Miyamoto, Yohei Matsumoto, Hanpei Koike, Tadayuki Matsumura, Kenichi Osada, Yaoko Nakagawa, Tadahiro Ohmi
Development of a CAD tool for 3D-FPGAs. 3DIC (2010)
Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. CICC (2009)
Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC (2009)
Masanao Yamaoka, Kenichi Osada, Takayuki Kawahara
A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. ESSCIRC (2008)
Masanao Yamaoka, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. ISSCC (2008)
Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi
Memory at VLSI Circuits Symposium. IEEE J. Solid State Circuits 43 (4) (2008)
Makoto Saen, Kenichi Osada, Satoshi Misaka, Tetsuya Yamada, Yoshitaka Tsujimoto, Yuki Kondo, Tatsuya Kamei, Yutaka Yoshida, Ei Nagahama, Yusuke Nitta, Takayasu Ito, Tadashi Kameyama, Naohiko Irie
Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. ISSCC (2007)
Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. ISSCC (2007)
Kenichi Osada, Takayuki Kawahara, Riichiro Takemura, Naoki Kitai, Norikatsu Takaura, Nozomu Matsuzaki, Kenzo Kurotsuchi, Hiroshi Moriya, Masahiro Moniwa
Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. CICC (2005)
Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh
A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. IEEE J. Solid State Circuits 40 (4) (2005)
Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada
A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. IEEE J. Solid State Circuits 40 (1) (2005)
Kenichi Osada, Naoki Kitai, Shiro Kamohara, Takayuki Kawahara
Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. CICC (2004)
Kiyoo Itoh, Kenichi Osada, Takayda Kawahara
Reviews and future prospects of low-voltage embedded RAMs. CICC (2004)
Kenichi Osada, Ken Yamaguchi, Yoshikazu Saitoh, Takayuki Kawahara
SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect. IEEE J. Solid State Circuits 39 (5) (2004)
Kiyoo Itoh, Kenichi Osada, Takayuki Kawahara
Low-Voltage Embedded RAMs - Current Status and Future Trends. PATMOS (2004)
Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi
0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. IEEE J. Solid State Circuits 39 (6) (2004)
Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, Koichiro Ishibashi
16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors. IEEE J. Solid State Circuits 38 (11) (2003)
Kenichi Osada, Jinuk Luke Shin, Masood Khan, Yude Liou, Karl Wang, Kenichi Shoji, Kenichi Kuroda, Shuji Ikeda, Koichiro Ishibashi
0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell. IEEE J. Solid State Circuits 36 (11) (2001)
Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. IEEE J. Solid State Circuits 31 (11) (1996)