A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme.
Akira KotabeKenichi OsadaNaoki KitaiMio FujiokaShiro KamoharaMasahiro MoniwaSadayuki MoritaYoshikazu SaitohPublished in: IEEE J. Solid State Circuits (2005)
Keyphrases
- low power
- high speed
- low cost
- power consumption
- cmos technology
- low voltage
- energy dissipation
- silicon dioxide
- single chip
- high power
- wireless transmission
- vlsi architecture
- digital signal processing
- low power consumption
- power reduction
- power system
- logic circuits
- real time
- vlsi circuits
- power management
- power dissipation
- liquid crystal
- leakage current
- field effect transistors
- power supply
- image sensor
- parallel computing