Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration.
Kiichi NiitsuYoshinori KohamaYasufumi SugimoriKazutaka KasugaKenichi OsadaNaohiko IrieHiroki IshikuroTadahiro KurodaPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2010)
Keyphrases
- low power
- low cost
- high speed
- experimental verification
- single chip
- power consumption
- low power consumption
- mixed signal
- cmos technology
- signal processor
- power dissipation
- nm technology
- image sensor
- digital signal processing
- ultra low power
- high power
- wireless transmission
- hardware and software
- real time
- vlsi circuits
- power saving
- power reduction
- logic circuits
- vlsi architecture
- cmos image sensor
- delay insensitive
- digital camera
- signal processing
- image processing