Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration.
Kiichi NiitsuYasufumi SugimoriYoshinori KohamaKenichi OsadaNaohiko IrieHiroki IshikuroTadahiro KurodaPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2011)
Keyphrases
- low power
- power consumption
- high speed
- power reduction
- power dissipation
- high power
- cmos technology
- low cost
- vlsi circuits
- logic circuits
- mixed signal
- power saving
- power management
- delay insensitive
- single chip
- energy saving
- vlsi architecture
- low power consumption
- wireless transmission
- ultra low power
- asynchronous circuits
- power line