A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation.
Shigenobu KomatsuMasanao YamaokaMasao MorimotoNoriaki MaedaYasuhisa ShimazakiKenichi OsadaPublished in: CICC (2009)
Keyphrases
- multistage
- low power
- power reduction
- power consumption
- cmos technology
- low cost
- high speed
- nm technology
- production system
- single chip
- high power
- single stage
- wireless transmission
- stochastic optimization
- lot sizing
- low voltage
- dynamic programming
- digital signal processing
- stochastic programming
- vlsi architecture
- power saving
- optimal policy
- low power consumption
- peer to peer
- vlsi circuits
- logic circuits
- image sensor
- leakage current
- assembly systems
- real time
- lot streaming
- ultra low power
- mixed signal
- interconnection networks
- power management
- power dissipation