Masao Morimoto

Publication Activity (10 Years)

Years Active: 2002-2020
Publications (10 Years): 4

Top Topics

Cmos Technology

Power Consumption

Top Venues

Publications

Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka
A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier. VLSI Circuits (2020)
Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, Masao Morimoto, Makoto Yabuuchi, Yuichiro Ishii, Shinji Tanaka
Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit. VLSI Circuits (2020)
Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka
12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM. VLSI Circuits (2018)
Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii
28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. A-SSCC (2016)
Yasumasa Tsukamoto, Masao Morimoto, Makoto Yabuuchi, Miki Tanaka, Koji Nii
ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology. VLSIC (2015)
Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. ISSCC (2014)
Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki
A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS. IEEE J. Solid State Circuits 48 (4) (2013)
Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Yasuhisa Shimazaki
A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS. VLSIC (2012)
Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. CICC (2009)
Masao Morimoto, Makoto Nagata, Kazuo Taki
Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations. IEICE Trans. Electron. (4) (2007)
Masao Morimoto, Yoshinori Tanaka, Makoto Nagata, Kazuo Taki
Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Masao Morimoto, Makoto Nagata, Kazuo Taki
High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition. IEICE Trans. Electron. (10) (2005)
Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. CICC (2002)