Yuichiro Ishii

Publication Activity (10 Years)

Years Active: 2007-2024
Publications (10 Years): 12

Top Topics

Power Reduction

Dynamic Random Access Memory

Top Venues

IEEE J. Solid State Circuits

Publications

Yumito Aoyagi, Koji Nii, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. IEEE J. Solid State Circuits 59 (4) (2024)
Yoshisato Yokoyama, Koji Nii, Yuichiro Ishii, Shinji Tanaka, Kazutoshi Kobayashi
Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing. IEEE J. Solid State Circuits 58 (7) (2023)
Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang
A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. VLSI Technology and Circuits (2023)
Yoshisato Yokoyama, Yuichiro Ishii, Koji Nii, Kazutoshi Kobayashi
Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs. IEEE Trans. Very Large Scale Integr. Syst. 29 (7) (2021)
Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, Masao Morimoto, Makoto Yabuuchi, Yuichiro Ishii, Shinji Tanaka
Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit. VLSI Circuits (2020)
Yoshisato Yokoyama, Kenji Goto, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Yoshiki Tsujihashi, Yuichiro Ishii
A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU. A-SSCC (2019)
Yuichiro Ishii, Hiroki Yamamoto, Sungi Kim, Yusuke Ikemoto
Development of the experimental system that can acquire the gait data online in a quadruped robot. MHS (2018)
Yoshisato Yokoyama, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Makoto Yabuuchi, Yuichiro Ishii, Koji Nii
40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications. A-SSCC (2018)
Hiroki Yamamoto, Yuichiro Ishii, Sungi Kim, Yusuke Ikemoto
Decomposition of Movement Data of Quadruped Robot by Using Autoencoder. ROBIO (2018)
Yoshisato Yokoyama, Yuichiro Ishii, Haruyuki Okuda, Koji Nii
A dynamic power reduction in synchronous 2RW 8T dual-port SRAM by adjusting wordline pulse timing with same/different row access mode. A-SSCC (2017)
Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii
28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry. A-SSCC (2016)
Makoto Yabuuchi, Yohei Sawada, Toshiaki Sano, Yuichiro Ishii, Shinji Tanaka, Miki Tanaka, Koji Nii
16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time. VLSI Circuits (2016)
Yoshisato Yokoyama, Yuichiro Ishii, Toshihiro Inada, Koji Tanaka, Miki Tanaka, Yoshiki Tsujihashi, Koji Nii
A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU. A-SSCC (2015)
Shinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Toshiaki Sano, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato
A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. VLSIC (2014)
Yoshisato Yokoyama, Yuichiro Ishii, Koji Tanaka, Tatsuya Fukuda, Yoshiki Tsujihashi, Atsushi Miyanishi, Shinobu Asayama, Keiichi Maekawa, Kazutoshi Shiba, Koji Nii
40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues. A-SSCC (2014)
Yoshisato Yokoyama, Yuichiro Ishii, Hidemitsu Kojima, Atsushi Miyanishi, Yoshiki Tsujihashi, Shinobu Asayama, Kazutoshi Shiba, Koji Tanaka, Tatsuya Fukuda, Koji Nii, Kazumasa Yanagisawa
40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU. ISQED (2014)
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Yasumasa Tsukamoto, Yuichiro Ishii, Tetsuya Matsumura, Yoshio Matsuda
A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry. ISQED (2013)
Koji Nii, Yasumasa Tsukamoto, Yuichiro Ishii, Makoto Yabuuchi, Hidehiro Fujiwara, Kazuyoshi Okamoto
A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. Asian Test Symposium (2012)
Yuichiro Ishii, Yasumasa Tsukamoto, Koji Nii, Hidehiro Fujiwara, Makoto Yabuuchi, Koji Tanaka, Shinji Tanaka, Yasuhisa Shimazaki
A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs. ISSCC (2012)
Yasumasa Tsukamoto, Takeshi Kida, T. Yamaki, Yuichiro Ishii, Koji Nii, Koji Tanaka, Shinji Tanaka, Yuji Kihara
Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs. CICC (2011)
Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, Kazumasa Yanagisawa
A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues. IEEE J. Solid State Circuits 46 (11) (2011)
Kumiko Tanaka-Ishii, Yuichiro Ishii
Multilingual phrase-based concordance generation in real-time. Inf. Retr. 10 (3) (2007)