A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU.
Yoshisato YokoyamaKenji GotoTomohiro MiuraYukari OuchiDaisuke NakamuraJiro IshikawaShunya NagataYoshiki TsujihashiYuichiro IshiiPublished in: A-SSCC (2019)
Keyphrases
- cost effective
- low power
- cmos technology
- low cost
- power consumption
- power reduction
- power dissipation
- hardware software co design
- dynamic random access memory
- hardware and software
- embedded systems
- low power consumption
- nm technology
- high speed
- cost effectiveness
- hw sw
- low voltage
- data center
- digital signal processing
- power saving
- power management
- parallel processing
- long term