A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU.

Yoshisato Yokoyama Kenji Goto Tomohiro Miura Yukari Ouchi Daisuke Nakamura Jiro Ishikawa Shunya Nagata Yoshiki Tsujihashi Yuichiro Ishii

Published in: A-SSCC (2019)