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Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing.

Yoshisato YokoyamaKoji NiiYuichiro IshiiShinji TanakaKazutoshi Kobayashi
Published in: IEEE J. Solid State Circuits (2023)
Keyphrases
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