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A cost effective test screening method on 40-nm 4-Mb embedded SRAM for low-power MCU.
Yoshisato Yokoyama
Yuichiro Ishii
Toshihiro Inada
Koji Tanaka
Miki Tanaka
Yoshiki Tsujihashi
Koji Nii
Published in:
A-SSCC (2015)
Keyphrases
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cost effective
low power
low cost
power consumption
high speed
computational complexity
real time