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A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline.
Shinji Tanaka
Yuichiro Ishii
Makoto Yabuuchi
Toshiaki Sano
Koji Tanaka
Yasumasa Tsukamoto
Koji Nii
Hirotoshi Sato
Published in:
VLSIC (2014)
Keyphrases
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power consumption
knowledge base
leakage current
cmos technology
positive and negative
low power
high speed
nm technology
data transmission
dynamic random access memory
variance reduction
random access memory
dual band
real time
low cost
power reduction