A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.
Koji NiiMakoto YabuuchiHidehiro FujiwaraYasumasa TsukamotoYuichiro IshiiTetsuya MatsumuraYoshio MatsudaPublished in: ISQED (2013)