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A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry.

Koji NiiMakoto YabuuchiHidehiro FujiwaraYasumasa TsukamotoYuichiro IshiiTetsuya MatsumuraYoshio Matsuda
Published in: ISQED (2013)
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