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Hong-Chen Cheng
Publication Activity (10 Years)
Years Active: 2012-2024
Publications (10 Years): 3
Top Topics
Random Access Memory
Design Considerations
Particle Filter
Power Consumption
Top Venues
ISSCC
VLSI Technology and Circuits
IEEE J. Solid State Circuits
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Publications
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Masaru Haraguchi
,
Yorinobu Fujino
,
Yoshisato Yokoyama
,
Ming-Hung Chang
,
Yu-Hao Hsu
,
Hong-Chen Cheng
,
Koji Nii
,
Yih Wang
,
Tsung-Yung Jonathan Chang
15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.
ISSCC
(2024)
Yumito Aoyagi
,
Koji Nii
,
Makoto Yabuuchi
,
Tomotaka Tanaka
,
Yuichiro Ishii
,
Yoshiaki Osada
,
Takaaki Nakazato
,
Isabel Wang
,
Yu-Hao Hsu
,
Hong-Chen Cheng
,
Hung-Jen Liao
,
Tsung-Yung Jonathan Chang
Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking.
IEEE J. Solid State Circuits
59 (4) (2024)
Yumito Aoyagi
,
Makoto Yabuuchi
,
Tomotaka Tanaka
,
Yuichiro Ishii
,
Yoshiaki Osada
,
Takaaki Nakazato
,
Koji Nii
,
Isabel Wang
,
Yu-Hao Hsu
,
Hong-Chen Cheng
,
Hung-Jen Liao
,
Tsung-Yung Jonathan Chang
A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.
VLSI Technology and Circuits
(2023)
Robin Lee
,
Jung-Ping Yang
,
Chia-En Huang
,
Chih-Chieh Chiu
,
Wei-Shuo Kao
,
Hong-Chen Cheng
,
Hong-Jen Liao
,
Jonathan Chang
RA) circuitry achieving 3x reduction on speed variation for single ended arrays.
VLSIC
(2012)