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15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture.

Masaru HaraguchiYorinobu FujinoYoshisato YokoyamaMing-Hung ChangYu-Hao HsuHong-Chen ChengKoji NiiYih WangTsung-Yung Jonathan Chang
Published in: ISSCC (2024)
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