Masanao Yamaoka

Publication Activity (10 Years)

Years Active: 2002-2021
Publications (10 Years): 22

Top Topics

Monte Carlo Method

Resource Sharing

Combinatorial Optimization

Top Venues

IEEE J. Solid State Circuits

Publications

Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits 56 (1) (2021)
Takashi Takemoto, Kasho Yamamoto, Chihiro Yoshimura, Masato Hayashi, Masafumi Tada, Hiroaki Saito, Mayumi Mashimo, Masanao Yamaoka
4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems. ISSCC (2021)
Kasho Yamamoto, Takashi Takemoto, Chihiro Yoshimura, Mayumi Mashimo, Masanao Yamaoka
A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems. A-SSCC (2021)
Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki
Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. Soft Comput. 25 (3) (2021)
Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. ISSCC (2020)
Chihiro Yoshimura, Masato Hayashi, Takashi Takemoto, Masanao Yamaoka
CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem. ASP-DAC (2020)
Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki
Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. CoRR (2020)
Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka
A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. IEEE J. Solid State Circuits 55 (1) (2020)
Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE (2019)
Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka
A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. ISSCC (2019)
Masato Hayashi, Takashi Takemoto, Chihiro Yoshimura, Masanao Yamaoka
A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems. VLSI Circuits (2019)
Daisuke Oku, Kotaro Terada, Masato Hayashi, Masanao Yamaoka, Shu Tanaka, Nozomu Togawa
A Fully-Connected Ising Model Embedding Method and Its Evaluation for CMOS Annealing Machines. IEICE Trans. Inf. Syst. (9) (2019)
Masanao Yamaoka, Takuya Okuyama, Masato Hayashi, Chihiro Yoshimura, Takashi Takemoto
CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems. CICC (2019)
Takashi Takemoto, Normann Mertig, Masato Hayashi, Saki Susa-Tanaka, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Tamiki Komatsuzaki, Masanao Yamaoka
FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search. ReConFig (2018)
Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
An Ising model mapping to solve rectangle packing problem. VLSI-DAT (2018)
Yuya Sugie, Yuki Yoshida, Normann Mertig, Takashi Takemoto, Hiroshi Teramoto, Atsuyoshi Nakamura, Ichigaku Takigawa, Shin-ichi Minato, Masanao Yamaoka, Tamiki Komatsuzaki
Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity. TPNC (2018)
Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Masanao Yamaoka
Implementation and Evaluation of FPGA-based Annealing Processor for Ising Model by use of Resource Sharing. Int. J. Netw. Comput. 7 (2) (2017)
Takuya Okuyama, Masato Hayashi, Masanao Yamaoka
An Ising Computer Based on Simulated Quantum Annealing by Path Integral Monte Carlo Method. ICRC (2017)
Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Masanao Yamaoka
FPGA-based Annealing Processor for Ising Model. CANDAR (2016)
Takuya Okuyama, Chihiro Yoshimura, Masato Hayashi, Masanao Yamaoka
Computing architecture to perform approximated simulated annealing for Ising models. ICRC (2016)
Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution. Int. J. Netw. Comput. 6 (2) (2016)
Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing. IEEE J. Solid State Circuits 51 (1) (2016)
Masato Hayashi, Masanao Yamaoka, Chihiro Yoshimura, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution. CANDAR (2015)
N. Sugii, G. Jurczak, Masanao Yamaoka, A. Molnar, J. Tham, T. Piliszczuk, O. Nalamasu, J. Hausner, Shu Tanaka, T. Yamauchi, S. Sivaram, C. Diaz, W. Dai
Technology/circuits joint evening panel discussion semiconductor industry in 2020: Evolution or revolution? VLSIC (2015)
Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno
24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing. ISSCC (2015)
Masaki Hamamoto, Masanao Yamaoka
An energy-efficient parallel-processing method based on master-hibernating DVFS. ISCAS (2014)
Chihiro Yoshimura, Masanao Yamaoka, Hidetaka Aoki, Hiroyuki Mizuno
Spatial computing architecture using randomness of memory cell stability under voltage control. ECCTD (2013)
Kiyoo Itoh, Masanao Yamaoka, Takashi Oshima
Adaptive Circuits for the 0.5-V Nanoscale CMOS Era. IEICE Trans. Electron. (3) (2010)
Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada
A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation. CICC (2009)
Masanao Yamaoka, Kenichi Osada, Takayuki Kawahara
A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. ESSCIRC (2008)
Masanao Yamaoka, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada
65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS. ISSCC (2008)
Kiyoo Itoh, Masashi Horiguchi, Masanao Yamaoka
Low-voltage limitations of memory-rich nano-scale CMOS LSIs. ESSCIRC (2007)
Masanao Yamaoka, Takayuki Kawahara
Operating-margin-improved SRAM with column-at-a-time body-bias control technique. ESSCIRC (2007)
Kiyoo Itoh, Masanao Yamaoka, Takayuki Kawahara
Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. ACM Great Lakes Symposium on VLSI (2007)
Masanao Yamaoka, Hidetoshi Onodera
A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design. SoCC (2006)
Masanao Yamaoka, Ryuta Tsuchiya, Takayuki Kawahara
SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors. IEEE J. Solid State Circuits 41 (11) (2006)
Masanao Yamaoka, Noriaki Maeda, Yoshihiro Shinozaki, Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa, Takayuki Kawahara
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. IEEE J. Solid State Circuits 41 (3) (2006)
Masanao Yamaoka, Yoshihiro Shinozaki, Noriaki Maeda, Yasuhisa Shimazaki, Kei Kato, Shigeru Shimada, Kazumasa Yanagisawa, Kenichi Osada
A 300-MHz 25-/spl mu/A/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor. IEEE J. Solid State Circuits 40 (1) (2005)
Makoto Ishikawa, Tatsuya Kamei, Yuki Kondo, Masanao Yamaoka, Yasuhisa Shimazaki, Motokazu Ozawa, Saneaki Tamaki, Mikio Furuyama, Tadashi Hoshi, Fumio Arakawa, Osamu Nishii, Kenji Hirose, Shinichi Yoshioka, Toshihiro Hattori
A 4500 MIPS/W, 86 µA Resume-Standby, 11 µA Ultra-Standby Application Processor for 3G Cellular Phones. IEICE Trans. Electron. (4) (2005)
Masanao Yamaoka, Kenichi Osada, Koichiro Ishibashi
0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme. IEEE J. Solid State Circuits 39 (6) (2004)
Masanao Yamaoka, Kazumasa Yanagisawa, Shoji Shukuri, Katsuhiro Norisue, Koichiro Ishibashi
A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit. IEEE J. Solid State Circuits 37 (5) (2002)