A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems.
Takashi TakemotoMasato HayashiChihiro YoshimuraMasanao YamaokaPublished in: IEEE J. Solid State Circuits (2020)
Keyphrases
- combinatorial optimization problems
- combinatorial optimization
- random access memory
- high speed
- single chip
- discrete optimization
- simulated annealing
- continuous optimization problems
- analog vlsi
- optimization problems
- processor core
- knapsack problem
- metaheuristic
- image sensor
- memory management
- memory subsystem
- processing elements
- focal plane
- chip design
- low cost
- traveling salesman problem
- memory access
- low latency
- job shop scheduling
- low power
- low voltage
- cmos image sensor
- ant colony optimization
- multithreading
- circuit design
- random access
- vehicle routing problem
- level parallelism
- dynamic random access memory
- direct memory access
- embedded dram
- gigabit ethernet
- ibm zenterprise
- power consumption
- genetic algorithm
- nm technology
- power dissipation
- minmax regret
- ibm power processor
- processing units
- main memory
- parallel processing
- clock frequency