Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes.
Yuya SugieYuki YoshidaNormann MertigTakashi TakemotoHiroshi TeramotoAtsuyoshi NakamuraIchigaku TakigawaShin-ichi MinatoMasanao YamaokaTamiki KomatsuzakiPublished in: CoRR (2020)
Keyphrases
- directed graph
- graph structure
- processing elements
- nodes of a graph
- massive graphs
- list scheduling
- high end
- graph embedding
- adjacency matrix
- weighted graph
- processing units
- undirected graph
- parallel architectures
- parallel architecture
- graph matching
- parallel processors
- densely connected
- parallel computation
- edge weights
- random graphs
- fully connected
- hardware and software
- connected graphs
- low cost
- simulated annealing
- search algorithm
- massively parallel
- parallel algorithm
- shortest path
- real time
- graph structures
- graph mining
- embedded processors
- hardware architecture
- computer systems
- real world graphs
- random walk
- attributed graphs
- multi core processors
- load balance
- semi supervised
- processor core
- parallel execution
- sparse representation
- vector space
- spanning tree
- real world networks
- multithreading
- small world
- parallel computing
- scheduling problem
- general purpose processors
- high dimensional
- signal processor
- graph mining algorithms