65nm Low-Power High-Density SRAM Operable at 1.0V under 3σ Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS.
Masanao YamaokaNoriaki MaedaYasuhisa ShimazakiKenichi OsadaPublished in: ISSCC (2008)
Keyphrases
- low power
- high density
- power consumption
- cmos technology
- high power
- data center
- low cost
- high speed
- nm technology
- low density
- power reduction
- close proximity
- single chip
- ultra low power
- real time
- thin film
- wireless transmission
- vlsi circuits
- low power consumption
- low voltage
- logic circuits
- digital signal processing
- mixed signal
- magnetic tape
- database systems
- vlsi architecture
- image sensor
- digital camera
- power management
- power dissipation
- rfid tags
- cost effective
- silicon on insulator
- dynamic random access memory
- data streams