Masao Yanagisawa

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 83

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

ASICON

APCCAS

ISCAS

Publications

Yirui Su, Masao Yanagisawa, Youhua Shi
Strategy for Improving Cycle of Maximized Energy Output of Triboelectric Nanogenerators. ICICDT (2023)
Jiaxiang Li, Masao Yanagisawa, Youhua Shi
An Area-Power-Efficient Multiplier-less Processing Element Design for CNN Accelerators. ASICON (2023)
Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi
Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow. IEEE Access 9 (2021)
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
Trojan-Net Classification for Gate-Level Hardware Design Utilizing Boundary Net Structures. IEICE Trans. Inf. Syst. (7) (2020)
Jinghao Ye, Masao Yanagisawa, Youhua Shi
A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters. APCCAS (2020)
Jinghao Ye, Masao Yanagisawa, Youhua Shi
Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2020)
Saki Tajima, Masao Yanagisawa, Youhua Shi
Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets. IEEE Trans. Circuits Syst. II Express Briefs (6) (2020)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design. IPSJ Trans. Syst. LSI Des. Methodol. 13 (2020)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation. LASCAS (2020)
Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
A Multiple Cyclic-Route Generation Method with Route Length Constraint Considering Point-of-Interests. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2019)
Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi
A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks. APCCAS (2019)
Jinghao Ye, Masao Yanagisawa, Youhua Shi
A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing. APCCAS (2019)
Jinghao Ye, Masao Yanagisawa, Youhua Shi
An Adder-Segmentation-based FIR for High Speed Signal Processing. ASICON (2019)
Yuri Usami, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
Bicycle Behavior Recognition Using 3-Axis Acceleration Sensor and 3-Axis Gyro Sensor Equipped with Smartphone. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2019)
Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE (2019)
Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. ISCAS (2019)
Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
An FPGA Implementation Method based on Distributed-register Architectures. IPSJ Trans. Syst. LSI Des. Methodol. 12 (2019)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels. ICECS (2019)
Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
A Robust Indoor/Outdoor Detection Method Based on Spatial and Temporal Features of Sparse GPS Measured Positions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2019)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Error Correction Coding of Stochastic Numbers Using BER Measurement. IOLTS (2019)
Siya Bao, Masao Yanagisawa, Nozomu Togawa
A Travel Decision Support Algorithm: Landmark Activity Extraction from Japanese Travel Comments. ICIS (best papers) (2019)
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
Scan-based Side-channel Attack against HMAC-SHA-256 Circuits Based on Isolating Bit-transition Groups Using Scan Signatures. IPSJ Trans. Syst. LSI Des. Methodol. 11 (2018)
Siya Bao, Masao Yanagisawa, Nozomu Togawa
Road-illuminance level inference across road networks based on Bayesian analysis. ICCE (2018)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. IOLTS (2018)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement. NGCAS (2018)
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
A hardware-Trojan classification method utilizing boundary net structures. ICCE (2018)
Mamoru Hirota, Ayumu Tsuboi, Masayuki Yokoyama, Masao Yanagisawa
Gesture recognition of air-tapping and its application to character input in VR space. SIGGRAPH ASIA Posters (2018)
Kotaro Terada, Daisuke Oku, Sho Kanamaru, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
An Ising model mapping to solve rectangle packing problem. VLSI-DAT (2018)
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis. IOLTS (2018)
Tomotaka Inoue, Kento Hasegawa, Yuki Kobayashi, Masao Yanagisawa, Nozomu Togawa
Designing Subspecies of Hardware Trojans and Their Detection Using Neural Network Approach. ICCE-Berlin (2018)
Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Tensei Nishimura, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
A Multiple Cyclic-Route Generation Method for Strolling Based on Point-of-Interests. ICCE-Berlin (2018)
Siya Bao, Masao Yanagisawa, Nozomu Togawa
Landmark Seasonal Travel Distribution and Activity Prediction Based on Language-specific Analysis. IEEE BigData (2018)
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation. ISCAS (2018)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
A Stayed Location Estimation Method for Sparse GPS Positioning Information Based on Positioning Accuracy and Short-Time Cluster Removal. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2018)
Sae Iwata, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
Robust Indoor/Outdoor Detection Method based on Sparse GPS Positioning Information. ICCE-Berlin (2018)
Masaru Oya, Masao Yanagisawa, Nozomu Togawa
Hardware Trojan Detection and Classification Based on Logic Testing Utilizing Steady State Learning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Yuri Usami, Kazuaki Ishikawa, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
Bicycle Behavior Recognition using Sensors Equipped with Smartphone. ICCE-Berlin (2018)
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
A loop structure optimization targeting high-level synthesis of fast number theoretic transform. ISQED (2018)
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2018)
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
Hardware Trojans classification for gate-level netlists using multi-layer neural networks. IOLTS (2017)
Yuki Yahagi, Masao Yanagisawa, Nozomu Togawa
Robust AES circuit design for delay variation using suspicious timing error prediction. ISOCC (2017)
Siya Bao, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa
A Safe and Comprehensive Route Finding Algorithm for Pedestrians Based on Lighting and Landmark Conditions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2017)
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
Trojan-feature extraction at gate-level netlists and its application to hardware-Trojan detection using random forest classifier. ISCAS (2017)
Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
A robust scan-based side-channel attack method against HMAC-SHA-256 circuits. ICCE-Berlin (2017)
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
Effective write-reduction method for MLC non-volatile memory. ISCAS (2017)
Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2017)
Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
Soft error tolerant latch designs with low power consumption (invited paper). ASICON (2017)
Masayuki Yokoyama, Ryohei Koyama, Masao Yanagisawa
An Evaluation of Hand-Force Prediction Using Artificial Neural-Network Regression Models of Surface EMG Signals for Handwear Devices. J. Sensors 2017 (2017)
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
Trojan-Net Feature Extraction and Its Application to Hardware-Trojan Detection for Gate-Level Netlists Using Random Forest. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Masaru Oya, Masao Yanagisawa, Nozomu Togawa
Hardware Trojan detection and classification based on steady state learning. IOLTS (2017)
Ayumu Tsuboi, Mamoru Hirota, Junki Sato, Masayuki Yokoyama, Masao Yanagisawa
A proposal for wearable controller device and finger gesture recognition using surface electromyography. SIGGRAPH ASIA (Posters) (2017)
Koki Igawa, Masao Yanagisawa, Nozomu Togawa
A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Siya Bao, Masao Yanagisawa, Nozomu Togawa
Personalized one-day travel with multi-nearby-landmark recommendation. ICCE-Berlin (2017)
Yuya Hirai, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
A selector-based FFT processor and its FPGA implementation. ISOCC (2017)
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
A Bitwidth-Aware High-Level Synthesis Algorithm Using Operation Chainings for Tiled-DR Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2017)
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
A Hardware-Trojan Classification Method Using Machine Learning at Gate-Level Netlists Based on Trojan Features. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Daiki Asai, Masao Yanagisawa, Nozomu Togawa
Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems. ASICON (2017)
Sae Iwata, Tomoyuki Nitta, Toshinori Takayama, Masao Yanagisawa, Nozomu Togawa
A stayed location estimation method for sparse GPS positioning information. GCCE (2017)
Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa
A low cost and high speed CSD-based symmetric transpose block FIR implementation. ASICON (2017)
Ryoya Momose, Tomoyuki Nitta, Masao Yanagisawa, Nozomu Togawa
An accurate indoor positioning algorithm using particle filter based on the proximity of bluetooth beacons. GCCE (2017)
Tomotaka Inoue, Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa
Designing hardware trojans and their detection based on a SVM-based approach. ASICON (2017)
Kento Hasegawa, Masaru Oya, Masao Yanagisawa, Nozomu Togawa
Hardware Trojans classification for gate-level netlists based on machine learning. IOLTS (2016)
Masaru Oya, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Masao Yanagisawa, Nozomu Togawa
Hardware-Trojans Rank: Quantitative Evaluation of Security Threats at Gate-Level Netlists by Pattern Matching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Daisuke Oku, Masao Yanagisawa, Nozomu Togawa
Implementation evaluation of scan-based attack against a Trivium cipher circuit. APCCAS (2016)
Masaru Oya, Masao Yanagisawa, Nozomu Togawa
Redesign for untrusted gate-level netlists. IOLTS (2016)
Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
A delay variation and floorplan aware high-level synthesis algorithm with body biasing. ISQED (2016)
Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
Rotator-based multiplexer network synthesis for field-data extractors. SoCC (2016)
Siya Bao, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
A safe and comprehensive route finding method for pedestrian based on lighting and landmark. GCCE (2016)
Ryoya Yano, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
Pedestrian navigation based on landmark recognition using glass-type wearable devices. GCCE (2016)
Koki Ito, Kazushi Kawamura, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
Bi-Partitioning Based Multiplexer Network for Field-Data Extractors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
A high-performance circuit design algorithm using data dependent approximation. ISOCC (2016)
Koki Igawa, Masao Yanagisawa, Nozomu Togawa
A Multi-Scenario High-Level Synthesis Algorithm for Variation-Tolerant Floorplan-Driven Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
A Highly-Adaptable and Small-Sized In-Field Power Analyzer for Low-Power IoT Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Koki Igawa, Masao Yanagisawa, Nozomu Togawa
Multi-scenario high-level synthesis for dynamic delay variation and its evaluation on FPGA platforms. IEICE Electron. Express 13 (18) (2016)
Keisuke Kono, Tomoyuki Nitta, Kazuaki Ishikawa, Masao Yanagisawa, Nozomu Togawa
Comprehensive deformed map generation for wristwatch-type wearable devices based on landmark-based partitioning. GCCE (2016)
Ryosuke Kitayama, Takashi Takenaka, Masao Yanagisawa, Nozomu Togawa
Scalable and small-sized power analyzer design with signal-averaging noise reduction for low-power IoT devices. ISCAS (2016)
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
In-situ Trojan authentication for invalidating hardware-Trojan functions. ISQED (2016)
Huiqian Jiang, Mika Fujishiro, Hirokazu Kodera, Masao Yanagisawa, Nozomu Togawa
Scan-Based Side-Channel Attack on the Camellia Block Cipher Using Scan Signatures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Siya Bao, Tomoyuki Nitta, Daisuke Shindou, Masao Yanagisawa, Nozomu Togawa
A landmark-based route recommendation method for pedestrian walking strategies. GCCE (2015)
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. ICCAD (2015)
Koki Ito, Yutaka Tamiya, Masao Yanagisawa, Nozomu Togawa
Partitioning-based multiplexer network synthesis for field-data extractors. SoCC (2015)
Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa
Clock skew estimate modeling for FPGA high-level synthesis and its application. ASICON (2015)
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
A floorplan-driven high-level synthesis algorithm with multiple-operation chainings based on path enumeration. ISCAS (2015)
Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa
A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation. ASICON (2015)
Hiroyuki Akasaka, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating. Inf. Media Technol. 10 (1) (2015)
Koichi Fujiwara, Kazushi Kawamura, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa
A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa
A High-Level Synthesis Algorithm with Inter-Island Distance Based Operation Chainings for RDR Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
A score-based classification method for identifying hardware-trojans at gate-level netlists. DATE (2015)
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
A bit-write reduction method based on error-correcting codes for non-volatile memories. ASP-DAC (2015)
Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. SoCC (2015)

Masao Yanagisawa.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Masao Yanagisawa