Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating.
Hiroyuki AkasakaShin-ya AbeMasao YanagisawaNozomu TogawaPublished in: Inf. Media Technol. (2015)
Keyphrases
- multistage
- energy efficient
- high level synthesis
- wireless sensor networks
- energy consumption
- parallel architecture
- sensor networks
- energy efficiency
- power consumption
- dynamic programming
- base station
- lot sizing
- real time
- routing protocol
- data transmission
- energy saving
- parallel processing
- cost effective
- hardware implementation
- optimal policy
- high speed
- design space exploration
- image processing