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Hiroyuki Akasaka
Publication Activity (10 Years)
Years Active: 2012-2014
Publications (10 Years): 0
Top Topics
Power Reduction
Sensor Nodes
Energy Efficiency
Transaction Processing
Top Venues
IPSJ Trans. Syst. LSI Des. Methodol.
ISOCC
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Publications
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Hiroyuki Akasaka
,
Shin-ya Abe
,
Masao Yanagisawa
,
Nozomu Togawa
Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating.
IPSJ Trans. Syst. LSI Des. Methodol.
7 (2014)
Hiroyuki Akasaka
,
Shin-ya Abe
,
Masao Yanagisawa
,
Nozomu Togawa
Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling.
IPSJ Trans. Syst. LSI Des. Methodol.
6 (2013)
Hiroyuki Akasaka
,
Masao Yanagisawa
,
Nozomu Togawa
Energy-efficient high-level synthesis for HDR architectures with clock gating.
ISOCC
(2012)