Energy-efficient high-level synthesis for HDR architectures with clock gating.
Hiroyuki AkasakaMasao YanagisawaNozomu TogawaPublished in: ISOCC (2012)
Keyphrases
- energy efficient
- high level synthesis
- power consumption
- wireless sensor networks
- energy efficiency
- energy consumption
- sensor networks
- parallel architecture
- base station
- multi hop
- power reduction
- data transmission
- sensor nodes
- energy saving
- routing protocol
- real time
- power dissipation
- routing algorithm
- ad hoc networks
- design space exploration
- image processing