Energy-efficient High-level Synthesis for HDR Architecture with Multi-stage Clock Gating.
Hiroyuki AkasakaShin-ya AbeMasao YanagisawaNozomu TogawaPublished in: IPSJ Trans. Syst. LSI Des. Methodol. (2014)
Keyphrases
- multistage
- energy efficient
- high level synthesis
- wireless sensor networks
- parallel architecture
- energy consumption
- sensor networks
- dynamic programming
- lot sizing
- energy efficiency
- optimal policy
- power consumption
- base station
- routing protocol
- mac protocol
- power reduction
- real time
- routing algorithm
- reinforcement learning
- sensor nodes
- processing units
- high speed
- machine learning