Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling.
Hiroyuki AkasakaShin-ya AbeMasao YanagisawaNozomu TogawaPublished in: Inf. Media Technol. (2013)
Keyphrases
- energy efficient
- high level synthesis
- wireless sensor networks
- energy consumption
- energy efficiency
- power consumption
- sensor networks
- scheduling algorithm
- scheduling problem
- base station
- parallel architecture
- concurrency control
- sensor nodes
- data transmission
- energy saving
- mac protocol
- design space exploration
- power reduction
- routing algorithm
- routing protocol
- database systems
- parallel machines
- power dissipation