Energy-efficient High-level Synthesis for HDR Architectures with Clock Gating Based on Concurrency-oriented Scheduling.
Hiroyuki AkasakaShin-ya AbeMasao YanagisawaNozomu TogawaPublished in: IPSJ Trans. Syst. LSI Des. Methodol. (2013)
Keyphrases
- energy efficient
- high level synthesis
- wireless sensor networks
- energy efficiency
- power consumption
- energy consumption
- sensor networks
- parallel architecture
- scheduling problem
- scheduling algorithm
- base station
- power reduction
- routing protocol
- sensor nodes
- concurrency control
- design space exploration
- database systems
- mac protocol
- energy saving
- parallel machines
- data transmission
- mobile agents
- response time
- transaction processing