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A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs.
Koichi Fujiwara
Kazushi Kawamura
Shin-ya Abe
Masao Yanagisawa
Nozomu Togawa
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2015)
Keyphrases
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detection algorithm
computational complexity
np hard
optimal solution
preprocessing
parallel implementation
learning algorithm
information systems
pattern recognition
k means
dynamic programming
embedded systems
hardware implementation
software implementation