Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs.
Koichi FujiwaraKazushi KawamuraMasao YanagisawaNozomu TogawaPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2016)