A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks.

Lin Ye Jinghao Ye Masao Yanagisawa Youhua Shi

Published in: APCCAS (2019)

Keyphrases

low power
single chip
low power consumption
low cost
high speed
power consumption
logic circuits
vlsi architecture
digital signal processing
power dissipation
design process
convolutional neural networks
image sensor
real time
mixed signal
gate array
cmos technology
data integrity
signal processing
ultra low power