Youhua Shi

Publication Activity (10 Years)

Years Active: 2003-2023
Publications (10 Years): 19

Top Topics

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Yirui Su, Masao Yanagisawa, Youhua Shi
Strategy for Improving Cycle of Maximized Energy Output of Triboelectric Nanogenerators. ICICDT (2023)
Jiaxiang Li, Masao Yanagisawa, Youhua Shi
An Area-Power-Efficient Multiplier-less Processing Element Design for CNN Accelerators. ASICON (2023)
Qianjin Wang, Yi Zhan, Bingqiang Liu, Jiajun Wu, Youhua Shi, Guoyi Yu, Chao Wang
A Reconfigurable Area and Energy Efficient Hardware Accelerator of Five High-order Operators for Vision Sensor Based Robot Systems. ICTA (2021)
Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi
Power-Efficient Deep Convolutional Neural Network Design Through Zero-Gating PEs and Partial-Sum Reuse Centric Dataflow. IEEE Access 9 (2021)
Jinghao Ye, Masao Yanagisawa, Youhua Shi
A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters. APCCAS (2020)
Jinghao Ye, Masao Yanagisawa, Youhua Shi
Faithfully Truncated Adder-Based Area-Power Efficient FIR Design with Predefined Output Accuracy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2020)
Saki Tajima, Masao Yanagisawa, Youhua Shi
Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets. IEEE Trans. Circuits Syst. II Express Briefs (6) (2020)
Lin Ye, Jinghao Ye, Masao Yanagisawa, Youhua Shi
A Zero-Gating Processing Element Design for Low-Power Deep Convolutional Neural Networks. APCCAS (2019)
Jinghao Ye, Masao Yanagisawa, Youhua Shi
A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing. APCCAS (2019)
Jinghao Ye, Masao Yanagisawa, Youhua Shi
An Adder-Segmentation-based FIR for High Speed Signal Processing. ASICON (2019)
Jinghao Ye, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
Static Error Analysis and Optimization of Faithfully Truncated Adders for Area-Power Efficient FIR Designs. ISCAS (2019)
Ken Hayamizu, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
Extension and Performance/Accuracy Formulation for Optimal GeAr-Based Approximate Adder Designs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Kento Hasegawa, Youhua Shi, Nozomu Togawa
Hardware Trojan Detection Utilizing Machine Learning Approaches. TrustCom/BigDataSE (2018)
Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
A Low Power Soft Error Hardened Latch with Schmitt-Trigger-Based C-Element. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Saki Tajima, Nozomu Togawa, Masao Yanagisawa, Youhua Shi
Soft error tolerant latch designs with low power consumption (invited paper). ASICON (2017)
Jinghao Ye, Youhua Shi, Nozomu Togawa, Masao Yanagisawa
A low cost and high speed CSD-based symmetric transpose block FIR implementation. ASICON (2017)
Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
A delay variation and floorplan aware high-level synthesis algorithm with body biasing. ISQED (2016)
Weiwei Shan, Wentao Dai, Youhua Shi, Peng Cao, Xiaoyan Xiang
Timing monitoring paths selection for wide voltage IC. IEICE Electron. Express 13 (8) (2016)
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
In-situ Trojan authentication for invalidating hardware-Trojan functions. ISQED (2016)
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
An Energy-Efficient Floorplan Driven High-Level Synthesis Algorithm for Multiple Clock Domains Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Masaru Oya, Youhua Shi, Noritaka Yamashita, Toshihiko Okamura, Yukiyasu Tsunoo, Satoshi Goto, Masao Yanagisawa, Nozomu Togawa
A Hardware-Trojans Identifying Method Based on Trojan Net Scoring at Gate-Level Netlists. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
An Effective Suspicious Timing-Error Prediction Circuit Insertion Algorithm Minimizing Area Overhead. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation. ASICON (2015)
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
A score-based classification method for identifying hardware-trojans at gate-level netlists. DATE (2015)
Koki Igawa, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures. SoCC (2015)
Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa
A low-power soft error tolerant latch scheme. ASICON (2015)
Masaru Oya, Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
Secure scan design using improved random order and its evaluations. APCCAS (2014)
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
An area-overhead-oriented monitoring-path selection algorithm for suspicious timing error prediction. APCCAS (2014)
Youhua Shi, Nozomu Togawa
In-situ timing monitoring methods for variation-resilient designs. APCCAS (2014)
Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
Throughput driven check point selection in suspicious timing error prediction based designs. LASCAS (2014)
Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
Concurrent faulty clock detection for crypto circuits against clock glitch based DFA. ISCAS (2013)
Youhua Shi, Hiroaki Igarashi, Nozomu Togawa, Masao Yanagisawa
Suspicious timing error prediction with in-cycle clock gating. ISQED (2013)
Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
Secure Scan Design with Dynamically Configurable Connection. PRDC (2013)
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Shin-ya Abe, Youhua Shi, Kimiyoshi Usami, Masao Yanagisawa, Nozomu Togawa
An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages. VLSI-DAT (2013)
Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
Dynamically changeable secure scan architecture against scan-based side channel attack. ISOCC (2012)
Yuta Atobe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit. APCCAS (2012)
Shin-ya Abe, Youhua Shi, Masao Yanagisawa, Nozomu Togawa
: multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures. IEICE Electron. Express 9 (17) (2012)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis. IEEE Trans. Very Large Scale Integr. Syst. 20 (1) (2012)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa
Scan-Based Attack on AES through Round Registers and Its Countermeasure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Improved Launch for Higher TDF Coverage With Fewer Test Patterns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (8) (2010)
Youhua Shi, Kenta Tokumitsu, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
VLSI implementation of a fast intra prediction algorithm for H.264/AVC encoding. APCCAS (2010)
Ryuta Nara, Hiroshi Atobe, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
State-dependent changeable scan architecture against scan-based side channel attacks. ISCAS (2010)
Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
). IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2009)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Design-for-secure-test for crypto cores. ITC (2009)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
X-Handling for Current X-Tolerant Compactors with More Unknowns and Maximal Compaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
GECOM: Test data compression combined with all unknown response masking. ASP-DAC (2008)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
A Unified Test Compression Technique for Scan Stimulus and Unknown Masking Data with No Test Loss. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
). ASP-DAC (2008)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Unknown response masking with minimized observable response loss and mask data. APCCAS (2008)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
A Secure Test Technique for Pipelined Advanced Encryption Standard. IEICE Trans. Inf. Syst. (3) (2008)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Design for Secure Test - A Case Study on Pipelined Advanced Encryption Standard. ISCAS (2007)
Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito
Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. DFT (2006)
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction. ASP-DAC (2006)
Youhua Shi, Nozomu Togawa, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
Selective Low-Care Coding: A Means for Test Data Compression in Circuits with Multiple Scan Chains. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura
Low Power Test Compression Technique for Designs with Multiple Scan Chain. Asian Test Symposium (2005)
Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki
Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. Asian Test Symposium (2004)
Youhua Shi, Zhe Zhang
Multiple test set generation method for LFSR-based BIST. ASP-DAC (2003)
Youhua Shi, Zhe Zhang, Shinji Kimura, Masao Yanagisawa, Tatsuo Ohtsuki
A Built-in Reseeding Technique for LFSR-Based Test Pattern Generation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)