Hideo Ito

Publication Activity (10 Years)

Years Active: 1991-2016
Publications (10 Years): 1

Top Topics

Real And Synthetic Datasets

Multipath Routing

Top Venues

IEICE Trans. Inf. Syst.

J. Electron. Test.

Int. J. Autom. Technol.

Publications

Xin Yuan, Takanori Yazawa, Hideo Ito, Tatsuki Otsubo, Yukio Maeda, Reiko Yamada
High-Efficiency Milling of Steam Turbine Blade. Int. J. Autom. Technol. 10 (6) (2016)
Wenpo Zhang, Kazuteru Namba, Hideo Ito
Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion. IEICE Trans. Inf. Syst. (10) (2014)
Wenpo Zhang, Kazuteru Namba, Hideo Ito
Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement. IEICE Trans. Inf. Syst. (3) (2014)
Kazuteru Namba, Takashi Katagiri, Hideo Ito
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop. J. Electron. Test. 29 (4) (2013)
Wenpo Zhang, Kazuteru Namba, Hideo Ito
Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF. IEICE Trans. Inf. Syst. (5) (2013)
Kazuteru Namba, Nobuhide Takashina, Hideo Ito
Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA. IEICE Trans. Inf. Syst. (8) (2013)
Kazuteru Namba, Takashi Katagiri, Hideo Ito
Dual-edge-triggered FF with timing error detection capability. DFT (2012)
Wenpo Zhang, Kazuteru Namba, Hideo Ito
Improving small-delay fault coverage for on-chip delay measurement. DFT (2012)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. IEEE Trans. Very Large Scale Integr. Syst. 20 (5) (2012)
Kazuteru Namba, Hideo Ito
Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits. IEEE Trans. Computers 60 (10) (2011)
Kiyonori Matsumoto, Kazuteru Namba, Hideo Ito
Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Kazuteru Namba, Hideo Ito
Construction of BILBO FF with Soft-Error-Tolerant Capability. IEICE Trans. Inf. Syst. (5) (2011)
Kazuteru Namba, Masatoshi Sakata, Hideo Ito
Single Event Induced Double Node Upset Tolerant Latch. DFT (2010)
Kazuteru Namba, Kengo Nakashima, Hideo Ito
Single-Event-Upset Tolerant RS Flip-Flop with Small Area. IEICE Trans. Inf. Syst. (12) (2010)
Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito
Quantitative Evaluation of Integrity for Remote System Using the Internet. PRDC (2010)
Kazuteru Namba, Takashi Ikeda, Hideo Ito
Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing. IEEE Trans. Very Large Scale Integr. Syst. 18 (9) (2010)
Kazuteru Namba, Hideo Ito
Soft Error Tolerant BILBO FF. DFT (2010)
Kazuteru Namba, Hideo Ito
Chiba Scan Delay Fault Testing with Short Test Application Time. J. Electron. Test. 26 (6) (2010)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. Asian Test Symposium (2010)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. IEICE Trans. Inf. Syst. (3) (2009)
Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito
A Delay Measurement Technique Using Signature Registers. Asian Test Symposium (2009)
Kazuteru Namba, Hideo Ito
Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2009)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
Design for Delay Fault Testability of 2-Rail Logic Circuits. IEICE Trans. Inf. Syst. (2) (2009)
Kazuteru Namba, Yoshikazu Matsui, Hideo Ito
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding. J. Electron. Test. 25 (1) (2009)
Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito
Dependability Evaluation for Internet-Based Remote Systems. PRDC (2009)
Kazuteru Namba, Hideo Ito
Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding. IEICE Trans. Inf. Syst. (2) (2009)
Takumi Hoshi, Kazuteru Namba, Hideo Ito
Testing of Switch Blocks in Three-Dimensional FPGA. DFT (2009)
Shuangyu Ruan, Kazuteru Namba, Hideo Ito
Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability. IEICE Trans. Inf. Syst. (8) (2009)
Shuangyu Ruan, Kazuteru Namba, Hideo Ito
Soft Error Hardened FF Capable of Detecting Wide Error Pulse. DFT (2008)
Yoichi Sasaki, Kazuteru Namba, Hideo Ito
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. J. Electron. Test. 24 (1-3) (2008)
Masato Kitakami, Bochuan Cai, Hideo Ito
A Checkpointing Method with Small Checkpoint Latency. IEICE Trans. Inf. Syst. (3) (2008)
Kazuteru Namba, Hideo Ito
Delay Fault Testability on Two-Rail Logic Circuits. DFT (2008)
Kazuteru Namba, Hideo Ito
Path Delay Fault Test Set for Two-Rail Logic Circuits. PRDC (2008)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. IPSJ Trans. Syst. LSI Des. Methodol. 1 (2008)
Toshinori Takabatake, Tomoki Nakamigawa, Hideo Ito
Connectivity of Generalized Hierarchical Completely-Connected Networks. J. Interconnect. Networks 9 (1/2) (2008)
Takashi Ikeda, Kazuteru Namba, Hideo Ito
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. DFT (2007)
Gang Zeng, Hideo Ito
Low-Cost IP Core Test Using Tri-Template-Based Codes. IEICE Trans. Inf. Syst. (1) (2007)
Abderrahim Doumar, Kentaroh Katoh, Hideo Ito
Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. DFT (2007)
Kazuteru Namba, Hideo Ito
Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding. ATS (2006)
Kentaroh Katoh, Hideo Ito
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. ETS (2006)
Yoichi Sasaki, Kazuteru Namba, Hideo Ito
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. DFT (2006)
Gang Zeng, Hideo Ito
Concurrent core test for SOC using shared test set and scan chain disable. DATE (2006)
Gang Zeng, Hideo Ito
Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree. IEICE Trans. Inf. Syst. (3) (2006)
Kazuteru Namba, Hideo Ito
Redundant Design for Wallace Multiplier. IEICE Trans. Inf. Syst. (9) (2006)
Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito
Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. DFT (2006)
Kazuteru Namba, Hideo Ito
Proposal of Testable Multi-Context FPGA Architecture. IEICE Trans. Inf. Syst. (5) (2006)
Gang Zeng, Hideo Ito
X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability. IEICE Trans. Inf. Syst. (7) (2005)
Gang Zeng, Hideo Ito
Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core. IEICE Trans. Inf. Syst. (5) (2005)
Kazuteru Namba, Hideo Ito
Design of Defect Tolerant Wallace Multiplier. PRDC (2005)
Gang Zeng, Hideo Ito
Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree. ICCD (2005)
Kazuteru Namba, Hideo Ito
Scan Design for Two-Pattern Test without Extra Latches. IEICE Trans. Inf. Syst. (12) (2005)
Kazuteru Namba, Hideo Ito
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation. IEICE Trans. Inf. Syst. (9) (2005)
Kentaroh Katoh, Abderrahim Doumar, Hideo Ito
Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. IOLTS (2005)
Manabu Sueishi, Masato Kitakami, Hideo Ito
Fault-Tolerant Message Switching Based on Wormhole Switching and Backtracking. PRDC (2004)
Gang Zeng, Hideo Ito
Non-Intrusive Test Compression for SOC Using Embedded FPGA Core. DFT (2004)
Gang Zeng, Hideo Ito
Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core. VTS (2004)
Abderrahim Doumar, Hideo Ito
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. IEEE Trans. Very Large Scale Integr. Syst. 11 (3) (2003)
Gang Zeng, Hideo Ito
Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core. DFT (2003)
Toshinori Takabatake, Masato Kitakami, Hideo Ito
A Fault-tolerant Routing Strategy for Generalized Hierarchical Completely-connected Networks. IASTED PDCS (2002)
Toshinori Takabatake, Masato Kitakami, Hideo Ito
Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks. PRDC (2002)
Lihong Tong, Kazuki Suzuki, Hideo Ito
Optimal Seed Generation for Delay Fault Detection BIST. Asian Test Symposium (2002)
Masato Kitakami, Shunji Kubota, Hideo Ito
Fault-Tolerance of Functional Programs Based on the Parallel Graph Reduction. PRDC (2001)
Toshinori Takabatake, Masato Kitakami, Hideo Ito
Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks. PRDC (2001)
Abderrahim Doumar, Hideo Ito
Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. DFT (2000)
Abderrahim Doumar, Hideo Ito
Testing approach within FPGA-based fault tolerant systems. Asian Test Symposium (2000)
Toshinori Takabatake, Keiichi Kaneko, Hideo Ito
Generalized Hierarchical Completely-Connected Networks. ISPAN (1999)
Abderrahim Doumar, Toshiaki Ohmameuda, Hideo Ito
Design of an automatic testing for FPGAs. ETW (1999)
Abderrahim Doumar, Satoshi Kaneko, Hideo Ito
Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. DFT (1999)
Mikio Yagi, Keiichi Kaneko, Hideo Ito
LLT and LTn Schemes: Error Recovery Schemes in Mobile Environments. PRDC (1999)
Keiichi Kaneko, Hideo Ito
Fault-Tolerant Routing Algorithms for Hypercube Networks. IPPS/SPDP (1999)
Abderrahim Doumar, Hideo Ito
Testing the Logic Cells and Interconnect Resources for FPGAs. Asian Test Symposium (1999)
Abderrahim Doumar, Hideo Ito
An Automatic Testing and Diagnosis for FPGAs. PRDC (1999)
Hammadi Nait-Charif, Hideo Ito
Improving the Performance of Feedforward Neural Networks by Noise Injection into Hidden Neurons. J. Intell. Robotic Syst. 21 (2) (1998)
Hideo Ito, Takashi Yagi
Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks. DFT (1994)
Hideo Ito
A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. DFT (1993)
Hideo Ito, Nobuyuki Suzuki
A hypercube design on wafer-scale integration. Systems and Computers in Japan 22 (4) (1991)