Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths.

Kentaroh Katoh Kazuteru Namba Hideo Ito

Published in: IEICE Trans. Inf. Syst. (2009)

Keyphrases

circuit design
case study
building blocks
fault detection
design methodology
power dissipation
chip design
database
neural network
website
knowledge based systems
fault diagnosis
power consumption