Kentaroh Katoh

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 6

Top Topics

Fpga Implementation

Data Conversion

Top Venues

J. Electron. Test.

IEICE Electron. Express

Publications

Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Shuhei Yamamoto, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi
Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion. ITC (2023)
Shogo Katayama, Takayuki Nakatani, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Anna Kuwana, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi
Low distortion sine wave generator with simple harmonics cancellation circuit and filter for analog device testing. IEICE Electron. Express 20 (1) (2023)
Kentaroh Katoh, Shuhei Yamamoto, Zheming Zhao, Yujie Zhao, Shogo Katayama, Anna Kuwana, Takayuki Nakatani, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
A Physically Unclonable Function Using Time-to-Digital Converter with Linearity Self-Calibration and its FPGA Implementation. ITC-Asia (2023)
Keno Sato, Takayuki Nakatani, Shogo Katayama, Daisuke Iimori, Gaku Ogihara, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Kazumi Hatayama, Haruo Kobayashi
High Precision Voltage Measurement System Utilizing Low-End ATE Resource and BOST. ATS (2022)
Chris Mangelsdorf, Manasa Madhvaraj, Salvador Mir, Manuel Barragán, Daisuke Iimori, Takayuki Nakatani, Shogo Katayama, Gaku Ogihara, Yujie Zhao, Jianglin Wei, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
Innovative Practices Track: Innovative Analog Circuit Testing Technologies. VTS (2022)
Yujie Zhao, Kentaroh Katoh, Anna Kuwana, Shogo Katayama, Jianglin Wei, Haruo Kobayashi, Takayuki Nakatani, Kazumi Hatayama, Keno Sato, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies. J. Electron. Test. 38 (1) (2022)
Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi
Erratum to: A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. J. Electron. Test. 31 (4) (2015)
Kentaroh Katoh, Kazuteru Namba
A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement. ISQED (2015)
Kentaroh Katoh, Yutaro Kobayashi, Takeshi Chujo, Junshan Wang, Ensi Li, Congbing Li, Haruo Kobayashi
A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. J. Electron. Test. 30 (6) (2014)
Haruo Kobayashi, Hitoshi Aoki, Kentaroh Katoh, Congbing Li
Analog/mixed-signal circuit design in nano CMOS era. IEICE Electron. Express 11 (3) (2014)
Ru Yi, Minghui Wu, Koji Asami, Haruo Kobayashi, Ramin Khatami, Atsuhiro Katayama, Isao Shimizu, Kentaroh Katoh
Digital Compensation for Timing Mismatches in Interleaved ADCs. Asian Test Symposium (2013)
Kentaroh Katoh, Yuta Doi, Satoshi Ito, Haruo Kobayashi, Ensi Li, Nobukazu Takai
An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators. Asian Test Symposium (2013)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. IEEE Trans. Very Large Scale Integr. Syst. 20 (5) (2012)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. Asian Test Symposium (2010)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. IEICE Trans. Inf. Syst. (3) (2009)
Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito
A Delay Measurement Technique Using Signature Registers. Asian Test Symposium (2009)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
Design for Delay Fault Testability of 2-Rail Logic Circuits. IEICE Trans. Inf. Syst. (2) (2009)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. Inf. Media Technol. 3 (4) (2008)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. IPSJ Trans. Syst. LSI Des. Methodol. 1 (2008)
Abderrahim Doumar, Kentaroh Katoh, Hideo Ito
Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. DFT (2007)
Kentaroh Katoh, Hideo Ito
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. ETS (2006)
Kentaroh Katoh, Abderrahim Doumar, Hideo Ito
Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. IOLTS (2005)