A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit.

Kentaroh Katoh Kazuteru Namba Hideo Ito

Published in: Asian Test Symposium (2010)

Keyphrases

power dissipation
high speed
phase locked loop
power consumption
low cost
low power
circuit design
evolvable hardware
chip design
database
data sets
evolutionary algorithm
input output
critical path