Kazuteru Namba

Publication Activity (10 Years)

Years Active: 2001-2023
Publications (10 Years): 25

Top Topics

Fault Tolerance

Error Correcting

Top Venues

IEEE Trans. Computers

IEICE Trans. Inf. Syst.

Publications

Ji Wu, Kazuteru Namba
SRAM-based efficiency memory model for quantized convolutional neural networks. ICCE-Taiwan (2023)
Keisuke Kozu, Yuya Tanabe, Masato Kitakami, Kazuteru Namba
Low Power Neural Network by Reducing SRAM Operating Voltage. IEEE Access 10 (2022)
Shogo Takahashi, Kazuteru Namba
A Double Node Upset tolerant SR latch using C-element. ICCE-TW (2022)
Tomohiro Ishii, Kazuteru Namba
Stuck-at Fault Tolerance in DNN Using Statistical data. PRDC (2022)
Keisuke Kozu, Kazuteru Namba
Relaxing device requirements for non-linearity in Deep Neural Networks accelerators with Phase Change Memory. ICCE-TW (2021)
Tomohiro Takahashi, Kazuteru Namba
Influence of Recognition Performance on Recurrent Neural Network Using Phase-Change Memory as Synapses. ICCE-TW (2020)
Kazuteru Namba
Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge. IEICE Trans. Inf. Syst. (4) (2020)
Yuta Yamamoto, Kazuteru Namba
Complete Double Node Upset Tolerant Latch Using C-Element. IEICE Trans. Inf. Syst. (10) (2020)
Kazuteru Namba, Fabrizio Lombardi
Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM). IEEE Trans. Computers 68 (2) (2019)
Shanshan Liu, Pedro Reviriego, Kazuteru Namba, Salvatore Pontarelli, Liyi Xiao, Fabrizio Lombardi
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells. DFT (2019)
Kazuteru Namba, Fabrizio Lombardi
On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Kazuteru Namba, Fabrizio Lombardi
A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits. IEEE Trans. Computers 67 (10) (2018)
Yuta Yamamoto, Kazuteru Namba
Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element. DFT (2018)
Josaphat Tetuko Sri Sumantyo, Nobuyoshi Imura, Shunsuke Onishi, Tetsuo Yasaka, Robertus Heru Triharjanto, Koichi Ito, Steven Gao, Kazuteru Namba, Katsumi Hattori, Fumio Yamazaki, Chiharu Hongo, Akira Kato, Daniele Perissin
L band circularly polarized SAR onboard microsatellite. IGARSS (2017)
Hiroki Ueno, Kazuteru Namba
Construction of a soft error (SEU) hardened Latch with high critical charge. DFT (2016)
Wei Wei, Kazuteru Namba, Fabrizio Lombardi
Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level. ACM Great Lakes Symposium on VLSI (2016)
Ri Cui, Kazuteru Namba
A Calibration Technique for DVMC with Delay Time Controllable Inverter. IPSJ Trans. Syst. LSI Des. Methodol. 9 (2016)
Kazuteru Namba, Fabrizio Lombardi
Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems. IEEE Trans. Computers 65 (6) (2016)
Wei Wei, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories. IEEE Trans. Computers 65 (3) (2016)
Kazuteru Namba, Fabrizio Lombardi
Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems. IEEE Trans. Computers 65 (12) (2016)
Kazuteru Namba, Fabrizio Lombardi
A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems. IEEE Trans. Multi Scale Comput. Syst. 2 (4) (2016)
Kazuteru Namba, Fabrizio Lombardi
Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM). IEEE Trans. Computers 64 (7) (2015)
Fabrizio Lombardi, Wei Wei, Kazuteru Namba
Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits. ACM Great Lakes Symposium on VLSI (2015)
Kazuteru Namba, Fabrizio Lombardi
Parallel Decodable Two-Level Unequal Burst Error Correcting Codes. IEEE Trans. Computers 64 (10) (2015)
Kentaroh Katoh, Kazuteru Namba
A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement. ISQED (2015)
Wenpo Zhang, Kazuteru Namba, Hideo Ito
Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion. IEICE Trans. Inf. Syst. (10) (2014)
Wei Wei, Kazuteru Namba, Fabrizio Lombardi
New 4T-based DRAM cell designs. ACM Great Lakes Symposium on VLSI (2014)
Wenpo Zhang, Kazuteru Namba, Hideo Ito
Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement. IEICE Trans. Inf. Syst. (3) (2014)
Wei Wei, Fabrizio Lombardi, Kazuteru Namba
Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance. DFT (2014)
Kazuteru Namba, Fabrizio Lombardi
A novel scheme for concurrent error detection of OLS parallel decoders. DFTS (2013)
Kazuteru Namba, Takashi Katagiri, Hideo Ito
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop. J. Electron. Test. 29 (4) (2013)
Kouta Maebashi, Kazuteru Namba, Masato Kitakami
Testing of switch blocks in TSV-reduced Three-Dimensional FPGA. DFTS (2013)
Wei Wei, Kazuteru Namba, Fabrizio Lombardi
Extending Non-Volatile Operation to DRAM Cells. IEEE Access 1 (2013)
Wenpo Zhang, Kazuteru Namba, Hideo Ito
Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF. IEICE Trans. Inf. Syst. (5) (2013)
Kazuteru Namba, Nobuhide Takashina, Hideo Ito
Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA. IEICE Trans. Inf. Syst. (8) (2013)
Kazuteru Namba, Takashi Katagiri, Hideo Ito
Dual-edge-triggered FF with timing error detection capability. DFT (2012)
Takieddine Sbiai, Kazuteru Namba
NoC Dynamically Reconfigurable as TAM. Asian Test Symposium (2012)
Wenpo Zhang, Kazuteru Namba, Hideo Ito
Improving small-delay fault coverage for on-chip delay measurement. DFT (2012)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. IEEE Trans. Very Large Scale Integr. Syst. 20 (5) (2012)
Kazuteru Namba, Hideo Ito
Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits. IEEE Trans. Computers 60 (10) (2011)
Kiyonori Matsumoto, Kazuteru Namba, Hideo Ito
Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Kazuteru Namba, Hideo Ito
Construction of BILBO FF with Soft-Error-Tolerant Capability. IEICE Trans. Inf. Syst. (5) (2011)
Kazuteru Namba, Masatoshi Sakata, Hideo Ito
Single Event Induced Double Node Upset Tolerant Latch. DFT (2010)
Kazuteru Namba, Kengo Nakashima, Hideo Ito
Single-Event-Upset Tolerant RS Flip-Flop with Small Area. IEICE Trans. Inf. Syst. (12) (2010)
Masato Kitakami, Hiroshi Konno, Kazuteru Namba, Hideo Ito
Quantitative Evaluation of Integrity for Remote System Using the Internet. PRDC (2010)
Kazuteru Namba, Takashi Ikeda, Hideo Ito
Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing. IEEE Trans. Very Large Scale Integr. Syst. 18 (9) (2010)
Kazuteru Namba, Hideo Ito
Soft Error Tolerant BILBO FF. DFT (2010)
Kazuteru Namba, Hideo Ito
Chiba Scan Delay Fault Testing with Short Test Application Time. J. Electron. Test. 26 (6) (2010)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. Asian Test Symposium (2010)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. IEICE Trans. Inf. Syst. (3) (2009)
Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito
A Delay Measurement Technique Using Signature Registers. Asian Test Symposium (2009)
Kazuteru Namba, Hideo Ito
Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2009)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
Design for Delay Fault Testability of 2-Rail Logic Circuits. IEICE Trans. Inf. Syst. (2) (2009)
Kazuteru Namba, Yoshikazu Matsui, Hideo Ito
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding. J. Electron. Test. 25 (1) (2009)
Masato Kitakami, Akihiro Katada, Kazuteru Namba, Hideo Ito
Dependability Evaluation for Internet-Based Remote Systems. PRDC (2009)
Kazuteru Namba, Hideo Ito
Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding. IEICE Trans. Inf. Syst. (2) (2009)
Takumi Hoshi, Kazuteru Namba, Hideo Ito
Testing of Switch Blocks in Three-Dimensional FPGA. DFT (2009)
Shuangyu Ruan, Kazuteru Namba, Hideo Ito
Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability. IEICE Trans. Inf. Syst. (8) (2009)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. Inf. Media Technol. 3 (4) (2008)
Shuangyu Ruan, Kazuteru Namba, Hideo Ito
Soft Error Hardened FF Capable of Detecting Wide Error Pulse. DFT (2008)
Yoichi Sasaki, Kazuteru Namba, Hideo Ito
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. J. Electron. Test. 24 (1-3) (2008)
Kazuteru Namba, Hideo Ito
Delay Fault Testability on Two-Rail Logic Circuits. DFT (2008)
Kazuteru Namba, Hideo Ito
Path Delay Fault Test Set for Two-Rail Logic Circuits. PRDC (2008)
Kentaroh Katoh, Kazuteru Namba, Hideo Ito
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. IPSJ Trans. Syst. LSI Des. Methodol. 1 (2008)
Takashi Ikeda, Kazuteru Namba, Hideo Ito
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. DFT (2007)
Kazuteru Namba, Eiji Fujiwara
Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings. Systems and Computers in Japan 38 (8) (2007)
Kazuteru Namba, Hideo Ito
Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding. ATS (2006)
Yoichi Sasaki, Kazuteru Namba, Hideo Ito
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. DFT (2006)
Kazuteru Namba, Hideo Ito
Redundant Design for Wallace Multiplier. IEICE Trans. Inf. Syst. (9) (2006)
Kazuteru Namba, Hideo Ito
Proposal of Testable Multi-Context FPGA Architecture. IEICE Trans. Inf. Syst. (5) (2006)
Kazuteru Namba, Hideo Ito
Design of Defect Tolerant Wallace Multiplier. PRDC (2005)
Kazuteru Namba, Hideo Ito
Scan Design for Two-Pattern Test without Extra Latches. IEICE Trans. Inf. Syst. (12) (2005)
Kazuteru Namba, Hideo Ito
Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation. IEICE Trans. Inf. Syst. (9) (2005)
Kazuteru Namba, Eiji Fujiwara
Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2002)
Kazuteru Namba, Eiji Fujiwara
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. DFT (2001)
Kazuteru Namba, Eiji Fujiwara
A class of systematic m-ary single-symbol error correcting codes. Systems and Computers in Japan 32 (6) (2001)