Low Power Neural Network by Reducing SRAM Operating Voltage.
Keisuke KozuYuya TanabeMasato KitakamiKazuteru NambaPublished in: IEEE Access (2022)
Keyphrases
- low power
- neural network
- power consumption
- power reduction
- low cost
- high speed
- energy dissipation
- low voltage
- power management
- single chip
- cmos technology
- low power consumption
- power system
- high power
- power saving
- wireless transmission
- digital signal processing
- vlsi architecture
- vlsi circuits
- operating point
- image sensor
- gate array
- power supply
- pattern recognition
- mixed signal
- power dissipation
- electric field