Design for Delay Fault Testability of 2-Rail Logic Circuits.

Kentaroh Katoh Kazuteru Namba Hideo Ito

Published in: IEICE Trans. Inf. Syst. (2009)

Keyphrases

logic circuits
power dissipation
functional decomposition
low power
logic synthesis
high speed
real time
design process
gate array
computer vision
case study
fuzzy logic
input output