Yong-Bin Kim

ORCID

Publication Activity (10 Years)

Years Active: 1997-2023
Publications (10 Years): 42

Top Venues

ISOCC

MWSCAS

ACM Great Lakes Symposium on VLSI

DFT

Publications

Yixuan He, Minsu Choi, Kyung-Ki Kim, Yong-Bin Kim
Low-Power Counters using Pathfinding Technique. ISOCC (2023)
Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
Modeling Truncation-Based Approximation Error in Stochastic Computing Circuits. ISOCC (2023)
Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
A Time-Domain Parallel Counter for Deep Learning Macro. ISOCC (2022)
Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
Time-Efficient Approximate Stochastic Computing for Medical Imaging Applications. ISOCC (2022)
Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
A Time-Domain Computing-In-Memory Micro using Ring Oscillator. ISOCC (2021)
Youngwook Lee, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
Stochastic Edge Detection for Fine-Grained Progressive Precision. ISOCC (2021)
Cheolhyeong Park, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
FPGA-based Scalable Road Image Stochastic Denosing Approach. ISOCC (2021)
Yixuan He, Yong-Bin Kim
A Stray-Insensitive Low-Power Capacitive Sensor Interface with Time-Compensation Technique. MWSCAS (2021)
Yixuan He, Minsu Choi, Yong-Bin Kim
A Tunable High-Gain Low-Noise Transimpedance Amplifier for Biosensing. MWSCAS (2020)
Elizabeth Amyouny, Yixuan He, Kyung Ki Kim, Yong-Bin Kim
Peak Current Control Boost Converter with Time-Multiplex. ISOCC (2020)
Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
Gate Diffusion Input Multi-Threshold Null Convention Logic Circuit Design Approach. ISOCC (2020)
Yixuan He, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
An Ultra-Low-Power Tunable Bump Circuit using Source-Degenerated Differential Transconductor. ISOCC (2020)
Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
Area Efficient Multi-Threshold Null Convenction Logic. ISOCC (2019)
Yixuan He, Kyung Ki Kim, Yong-Bin Kim
Evaluations of Electronic Neuron Model for Low Power VLSI Implementation. ISOCC (2019)
Gyunam Jeon, Kyung Ki Kim, Yong-Bin Kim
Standing Wave Oscillator Based Clock Distribution Minimizing Equivalent Capacitance for Process and Temperature variation. ISOCC (2019)
Prashanthi Metku, Minsu Choi, Kyung Ki Kim, Yong-Bin Kim
Optimization of Null Convenction Logic Using Gate Diffusion Input. ISOCC (2019)
Gyunam Jeon, Yong-Bin Kim
10 GHz Standing Wave Oscillator Based Clock Distribution Network Considering Distributed Capacitance. MWSCAS (2019)
Yun Seok Hong, Yong-Bin Kim
Low Power Digital Temperature Sensor Using Modified Inverter Interlaced Cascaded Delay Cell. MWSCAS (2018)
Gyunam Jeon, Yong-Bin Kim
Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor. MWSCAS (2018)
Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
Generalized Adaptive Variable Bit Truncation Method for Approximate Stochastic Computing. ISOCC (2018)
Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique. ISOCC (2018)
Yongsuk Choi, Gyunam Jeon, Yong-Bin Kim
Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme. Integr. 63 (2018)
Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
Low-power null convention logic design based on modified gate diffusion input technique. ISOCC (2017)
HeungJun Jeon, Kyung Ki Kim, Yong-Bin Kim
Fully Integrated on-Chip Switched DC-DC Converter for Battery-Powered Mixed-Signal SoCs. Symmetry 9 (1) (2017)
Gyunam Jeon, Yong-Bin Kim
speculative tap. ISOCC (2017)
Ramu Seva, Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
Variable bit truncation technique for approximate stochastic computing (ASC). ISOCC (2017)
Gyunam Jeon, Yong-Bin Kim
Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate. ACM Great Lakes Symposium on VLSI (2017)
Gyunam Jeon, Yong-Bin Kim
A 4Gb/s half-rate DFE with switched-cap and IIR summation for data correction. ISCAS (2017)
Yun Seok Hong, Yong-Bin Kim, Kyung Ki Kim
Time-domain temperature sensor based on interlaced hysteresis delay cells. ISOCC (2017)
Haiyang Zhu, Wenhua Yang, Gil Engel, Yong-Bin Kim
A Two-Parameter Calibration Technique Tracking Temperature Variations for Current Source Mismatch. IEEE Trans. Circuits Syst. II Express Briefs (4) (2017)
Jing Yang, Yong-Bin Kim
Global clock distribution on standing wave with CMOS active inductor loading. MWSCAS (2017)
Yong-Bin Kim
Integrated circuits design using carbon nanotube field effect transistor. ISOCC (2016)
Ramu Seva, Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
Approximate stochastic computing (ASC) for image processing applications. ISOCC (2016)
Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
Hybrid GDI-NCL for area/power reduction. ISOCC (2016)
Yongsuk Choi, Yong-Bin Kim, In-Seok Jung
A 100MS/s 10-bit Split-SAR ADC with Capacitor Mismatch Compensation Using Built-In Calibration. NATW (2016)
Chen Zhang, Gyunam Jeon, Yongsuk Choi, Yong-Bin Kim, Kyung Ki Kim
An Area Efficient 4Gb/s Half-Rate 3-Tap DFE with Current-Integrating Summer for Data Correction. NATW (2016)
Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
Parallel decoding for multi-stage BCH decoder. ISOCC (2016)
Wei Wei, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories. IEEE Trans. Computers 65 (3) (2016)
Yongsuk Choi, Yong-Bin Kim
A Novel On-Chip Impedance Calibration Method for LPDDR4 Interface between DRAM and AP/SoC. ACM Great Lakes Symposium on VLSI (2016)
Ho Joon Lee, Yong-Bin Kim
A process tolerant semi-self impedance calibration method for LPDDR4 memory controller. MWSCAS (2015)
Yongsuk Choi, Yong-Bin Kim
A 10-Gb/s receiver with a continuous-time linear equalizer and 1-tap decision-feedback equalizer. MWSCAS (2015)
Haiyang Zhu, Ron Kapusta, Yong-Bin Kim
Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2015)
Ho Joon Lee, Yong-Bin Kim, Kyung Ki Kim
Full custom implementation of a S-Box circuit architecture using power gated PLA structure. MWSCAS (2014)
In-Seok Jung, Yong-Bin Kim
A novel self-calibration scheme for 12-bit 50MS/s SAR ADC. MWSCAS (2014)
Ho Joon Lee, Yong-Bin Kim
An area efficient low power high speed S-Box implementation using power-gated PLA. ACM Great Lakes Symposium on VLSI (2014)
Yongsuk Choi, Chun-hsiang Chang, Hari Chauhan, In-Seok Jung, Marvin Onabajo, Yong-Bin Kim
A built-in calibration system to optimize third-order intermodulation performance of RF amplifiers. MWSCAS (2014)
Yongsuk Choi, Yong-Bin Kim
A novel mixed-signal self-calibration technique for baseband filters in systems-on-chip mobile transceivers. ACM Great Lakes Symposium on VLSI (2014)
Jing Lu, Yong-Bin Kim
A low power high resolution digital PWM with process and temperature calibrations for digital controlled DC-DC converters. ACM Great Lakes Symposium on VLSI (2014)
In-Seok Jung, Yong-Bin Kim
A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch. DFT (2014)
Siva Kotipalli, Yong-Bin Kim, Minsu Choi
Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance. J. Electr. Comput. Eng. 2014 (2014)
Hari Chauhan, Yongsuk Choi, Marvin Onabajo, In-Seok Jung, Yong-Bin Kim
Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Haiyang Zhu, Wenhua Yang, Nathan Egan, Yong-Bin Kim
Calibration technique tracking temperature for current-steering digital-to-analog converters. MWSCAS (2014)
Yongsuk Choi, Chun-hsiang Chang, In-Seok Jung, Marvin Onabajo, Yong-Bin Kim
A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA. DFT (2014)
Yongsuk Choi, HeungJun Jeon, Yong-Bin Kim
A switched-capacitor DC-DC converter using delta-sigma digital pulse frequency modulation control method. MWSCAS (2013)
Weifu Li, Yong-Bin Kim
+1 squarer design based on carbon nanotube technology. MWSCAS (2013)
Ho Joon Lee, Yong-Bin Kim
Low power Null Convention Logic circuit design based on DCVSL. MWSCAS (2013)
In-Seok Jung, Marvin Onabajo, Yong-Bin Kim
A 10-bit 64MS/s SAR ADC using variable clock period method. MWSCAS (2013)
Siva Pavan Kumar Kotipalli, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi
Design and evaluation of Side Channel Attack resistant asynchronous AES Round Function. MWSCAS (2012)
Jianping Gong, Yong-Bin Kim, Fabrizio Lombardi, Jie Han
Hardening a memory cell for low power operation by gate leakage reduction. DFT (2012)
Moon Seok Kim, Yong-Bin Kim, Kyung Ki Kim
All-digital phased-locked loop with local passive interpolation time-to-digital converter based on a tristate inverter. MWSCAS (2012)
Jun Wu, Yong-Bin Kim, Minsu Choi
Configurable logic block (CLB) design for Asynchronous Nanowire Crossbar system. MWSCAS (2012)
Jing Yang, Yong-Bin Kim
Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit. ACM Great Lakes Symposium on VLSI (2012)
He Qi, Yong-Bin Kim, Minsu Choi
+1 multiplier design using carbon-nanotube technology. MWSCAS (2012)
Edward Collins, In-Seok Jung, Yong-Bin Kim, Kyung Ki Kim
A design and integration of Parametric Measurement Unit on to a 600MHz DCL. ISOCC (2012)
In-Seok Jung, Yong-Bin Kim
A CMOS Low-Power Digital Polar Modulator System Integration for WCDMA Transmitter. IEEE Trans. Ind. Electron. 59 (2) (2012)
HeungJun Jeon, Yong-Bin Kim
A fully integrated switched-capacitor DC-DC converter with dual output for low power application. ACM Great Lakes Symposium on VLSI (2012)
Jun Wu, Yong-Bin Kim, Minsu Choi
Post-configuration repair strategy for asynchronous nanowire crossbar system. MWSCAS (2012)
Jing Lu, Jing Yang, Yong-Bin Kim, Joseph Ayers
Low power, high PVT variation tolerant central pattern generator design for a bio-hybrid micro robot. MWSCAS (2012)
Tina Marie Rookmaaker, Moon Seok Kim, Yong-Bin Kim
Design and analysis of the quadfferential amplifier. Microelectron. J. 43 (10) (2012)
In-Seok Jung, Yong-Bin Kim, Fabrizio Lombardi
A novel sort error hardened 10T SRAM cells for low voltage operation. MWSCAS (2012)
Yongsuk Choi, Yong-Bin Kim, Fabrizio Lombardi
Soft error masking latch for sub-threshold voltage operation. MWSCAS (2012)
In-Seok Jung, Yong-Bin Kim
A low stand-by power start-up circuit for SMPS PWM controller. ACM Great Lakes Symposium on VLSI (2012)
HeungJun Jeon, Yong-Bin Kim, Kyung Ki Kim
A novel 4-to-3 step-down on-chip SC DC-DC converter with reduced bottom-plate loss. MWSCAS (2012)
Ho Joon Lee, Yong-Bin Kim, Kyung Ki Kim
On-chip HBD sensor for nanoscale CMOS technology. MWSCAS (2012)
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors. IEEE Trans. Very Large Scale Integr. Syst. 19 (5) (2011)
Edward Collins, In-Seok Jung, Yong-Bin Kim, Kyung Ki Kim
A design approach of a Parametric Measurement Unit on to a 600MHz DCL. ISOCC (2011)
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset. ICCD (2011)
Jun Zhao, Yong-Bin Kim
A novel all-digital fractional-N frequency synthesizer architecture with fast acquisition and low spur. ISQED (2010)
HeungJun Jeon, Yong-Bin Kim
A CMOS low-power low-offset and high-speed fully dynamic latched comparator. SoCC (2010)
Janardhanan S. Ajit, Yong-Bin Kim, Minsu Choi
Performance assessment of analog circuits with carbon nanotube FET (CNFET). ACM Great Lakes Symposium on VLSI (2010)
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
8Gb/s capacitive low power and high speed 4-PWAM transceiver design. ACM Great Lakes Symposium on VLSI (2010)
HeungJun Jeon, Yong-Bin Kim
A low-offset high-speed double-tail dual-rail dynamic latched comparator. ACM Great Lakes Symposium on VLSI (2010)
Young Bok Kim, Yong-Bin Kim
High speed and low power transceiver design with CNFET and CNT bundle interconnect. SoCC (2010)
Jun Zhao, Yong-Bin Kim
A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops. VLSI Design 2010 (2010)
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
Read-out schemes for a CNTFET-based crossbar memory. ACM Great Lakes Symposium on VLSI (2010)
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems. IEEE Trans. Instrum. Meas. 59 (5) (2010)
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability. Integr. 43 (2) (2010)
Jiaping Hu, Yong-Bin Kim, Joseph Ayers
A 65nm CMOS ultra low power and low noise 131M front-end transimpedance amplifier. SoCC (2010)
Geunho Cho, Fabrizio Lombardi, Yong-Bin Kim
Modelling a CNTFET with Undeposited CNT Defects. DFT (2010)
Jun Wu, Yong-Bin Kim, Minsu Choi
Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems. ACM Great Lakes Symposium on VLSI (2010)
Cristiana Bolchini, Yong-Bin Kim
Guest Editorial. J. Electron. Test. 25 (1) (2009)
Kyung Ki Kim, Yong-Bin Kim
A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems. IEEE Trans. Very Large Scale Integr. Syst. 17 (4) (2009)
Kyung Ki Kim, Yong-Bin Kim, Fabrizio Lombardi
A Novel Statistical Timing and Leakage Power Characterization of Partially Depleted Silicon-on-Insulator Gates. IEEE Trans. Instrum. Meas. 58 (2) (2009)
Xiaojun Ma, Masoud Hashempour, Yong-Bin Kim, Fabrizio Lombardi
Errors in DNA Self-Assembly by Synthesized Tile Sets. DFT (2009)
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
Soft-Error Hardening Designs of Nanoscale CMOS Latches. VTS (2009)
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi
A Novel Hardened Design of a CMOS Memory Cell at 32nm. DFT (2009)
Stephen Frechette, Yong-Bin Kim, Fabrizio Lombardi
Checkpointing of Rectilinear Growth in DNA Self-Assembly. DFT (2008)
Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi
Monomer Control for Error Tolerance in DNA Self-Assembly. J. Electron. Test. 24 (1-3) (2008)
Kyung Ki Kim, Yong-Bin Kim
Standby power reduction using optimal supply voltage and body-bias voltage. IEICE Electron. Express 5 (15) (2008)
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
Low power 8T SRAM using 32nm independent gate FinFET technology. SoCC (2008)

Yong-Bin Kim.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Yong-Bin Kim