Soft-Error Hardening Designs of Nanoscale CMOS Latches.

Sheng Lin Yong-Bin Kim Fabrizio Lombardi

Published in: VTS (2009)

Keyphrases

low power
error rate
power consumption
low cost
high speed
power supply
error bounds
vlsi circuits
motion estimation
estimation error
nm technology
data sets
linear complexity
theoretical analysis
artificial neural networks
lower bound
neural network