High speed and low power transceiver design with CNFET and CNT bundle interconnect.
Young Bok KimYong-Bin KimPublished in: SoCC (2010)
Keyphrases
- high speed
- low power
- single chip
- ultra low power
- low power consumption
- power dissipation
- logic circuits
- digital signal processing
- wireless transmission
- vlsi architecture
- gate array
- power consumption
- low cost
- high power
- frame rate
- cmos technology
- power reduction
- mixed signal
- vlsi circuits
- real time
- image sensor
- design methodology
- phase locked loop
- cmos image sensor
- wireless networks
- design process
- image processing