Hardening a memory cell for low power operation by gate leakage reduction.
Jianping GongYong-Bin KimFabrizio LombardiJie HanPublished in: DFT (2012)
Keyphrases
- low power
- cmos technology
- nm technology
- power consumption
- high speed
- low cost
- power reduction
- power dissipation
- high power
- single chip
- logic circuits
- digital signal processing
- wireless transmission
- low power consumption
- vlsi architecture
- image sensor
- random access
- low voltage
- real time
- vlsi circuits
- leakage current
- ultra low power
- delay insensitive
- main memory
- signal processing
- wireless sensor networks