A CMOS low-power low-offset and high-speed fully dynamic latched comparator.
HeungJun JeonYong-Bin KimPublished in: SoCC (2010)
Keyphrases
- low power
- high speed
- power consumption
- low power consumption
- low cost
- single chip
- high power
- wireless transmission
- vlsi circuits
- vlsi architecture
- frame rate
- cmos technology
- digital signal processing
- power reduction
- logic circuits
- image sensor
- delay insensitive
- focal plane
- real time
- gate array
- ultra low power
- data flow
- message passing
- signal processing
- image processing