Low-power side-channel attack-resistant asynchronous S-box design for AES cryptosystems.
Jun WuYong-Bin KimMinsu ChoiPublished in: ACM Great Lakes Symposium on VLSI (2010)
Keyphrases
- low power
- block cipher
- secret key
- s box
- single chip
- high speed
- logic circuits
- low cost
- low power consumption
- power consumption
- countermeasures
- vlsi architecture
- digital signal processing
- gate array
- power analysis
- delay insensitive
- real time
- smart card
- mixed signal
- cmos technology
- lightweight
- power dissipation
- authentication scheme
- differential equations
- power reduction
- ultra low power
- authentication protocol
- efficient implementation
- fault model