An area efficient low power high speed S-Box implementation using power-gated PLA.
Ho Joon LeeYong-Bin KimPublished in: ACM Great Lakes Symposium on VLSI (2014)
Keyphrases
- low power
- high speed
- power consumption
- high power
- vlsi architecture
- ultra low power
- low cost
- signal processor
- single chip
- cmos technology
- power dissipation
- s box
- efficient implementation
- vlsi circuits
- power saving
- cost effective
- low power consumption
- digital signal processing
- logic circuits
- power reduction
- energy dissipation
- gate array
- multi channel