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An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection.
Kentaroh Katoh
Kazuteru Namba
Hideo Ito
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2012)
Keyphrases
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defect detection
small number
low cost
neural network
high speed
high density
power dissipation