Path Delay Fault Test Set for Two-Rail Logic Circuits.
Kazuteru NambaHideo ItoPublished in: PRDC (2008)
Keyphrases
- test set
- logic circuits
- low power
- power dissipation
- high speed
- error rate
- training set
- functional decomposition
- fault diagnosis
- test data
- tunnel diode
- power consumption
- gate array
- class distribution
- evaluation methodology
- low cost
- training data
- data sets
- boolean functions
- test cases
- shortest path
- logic synthesis
- digital signal processing
- training and test sets
- machine learning
- neural network